Electrostatic discharge (ESD) is a momentary and sudden electric current that flows when an excess of electric charge stored on an electrically insulated structure finds a path to another structure at a different electrical potential, such as ground. ESD, its power consumption and efficient use of semiconductor real estate to protect integrated circuits (ICs) are particularly serious concerns with microelectronic devices. In most cases, the ICs in these devices are not repairable if affected by an ESD event. The shrinking size of modern electronics demands that ICs, complete with ESD protection, fit into a small package.
It is common in IC design to include ESD protection, in the form of a “clamping” circuit, to the terminals that receive an operating voltage for driving an IC chip, or portion thereof. A voltage clamp ensures that a sudden surge in voltage from an ESD event can be safely discharged so that no damage results to the internal active devices of the integrated circuit. The clamping circuit, which holds the voltage across the power supply terminals to the nominal power supply voltage, often requires one or more relatively very large field-effect transistors, or “BigFETs,” capable of discharging the electrical current produced from an ESD event that, however brief, can result in peak currents and voltages many times the operating voltage of the IC.
When an ESD potential occurs across the power supply and ground terminals, each BigFET is opened so as to conduct the ESD current, thereby clamping the power supply terminal voltage. Each BigFET is biased on when a gate driving circuit connected to the gate of that BigFET switches to a level to render the device conducting to rapidly discharge the ESD event. An RC timing circuit, also connected across the power supply and ground terminals, triggers the gate driving circuit during an ESD event.
Achieving performance gains while limiting power consumption requires aggressive scaling of transistor gate length, oxide thickness and supply voltage. Some conventional circuit applications, such as analog circuits and programmable fuses, require supply voltages greater than the native transistor voltage. These applications can create oxide reliability problems if classical RC-triggered power clamps are used for ESD protection of the high-voltage pins. Classical power clamps use a single thin oxide core or thick oxide I/O transistor (a BigFET) as the ESD current conducting device between VDD and ground. The gate oxide can potentially be damaged during high-voltage standby or during an ESD event.
FIG. 5 shows a conventional stacked power clamp 500 having a BigFET stack 504 made of two BigFETs 508, 512 electrically connected across VDD and ground pins 516, 520 via a middle node 524. A pair of inverter chains 528, 532, which are responsive to corresponding respective RC triggers 536, 540, drive the corresponding respective gates 508A, 512A of BigFETs 508, 512. In this design, inverter chains 528, 532 and RC triggers 536, 540 are connected across VDD and ground pins 516, 520 via middle node 524. As seen in FIG. 6, because the design of conventional power clamp 500 of FIG. 5 requires BigFET stack 504 to be connected to middle node 524, the physical instantiation 600 of this BigFET stack requires a diffusion contact region 604 between gates 508A, 512A. Because BigFETs 508, 512 need to be large to handle the high currents of an ESD event, diffusion contact region 604 is relatively very large and takes up quite a bit of chip area.
Stacked power clamps, i.e., power clamps having BigFETs connected in series with one another across the VDD and ground pins, are used for maximum gate reliability if no special high-voltage tolerant devices are available in the technology. Either thin oxide or thick oxide FETS may be used in the BigFET stack, depending on the applicable supply voltage. In a stacked power clamp, it would be preferred to lay out the stacked BigFETs in such a way that no diffusion contacts exist between the gates for significant area efficiency improvement. However, simply doing so for stacked NFET-based power clamps may cause serious turn-on delay in the bottom BigFET, because its gate will then be pulled up by the resistive voltage divider, whose large resistance (typically on the order of 500 kΩ) cannot quickly charge the high gate capacitance load.